Changes by: Jason Hickey (jyh at cs.caltech.edu)
Date: 2003-03-20 22:50:59 -0800 (Thu, 20 Mar 2003)
Revision: 4202
Log message:

      The problem with alpha-equality was because some MOVs _must_
      be coalesced.  Specifically, Let{Register{v}, v. e['v]} must
      be coalesced.
      
      This makes the first successful register allocation of the fib
      program.
      
      What's left:
         1. Functions must use a standard calling convention, rather
            than having the allocator choose locations of arguments
            at random.
         2. The LetReg[reg:s]{'src; v. 'e[v]} requires that v be the
            specific register mentioned in the parameter.  The register
            allocator currently ignores them.
      
      Once that's done, we need to pull the runtime from the class version
      of fjava, and try compiling for real.
      

Changes  Path
+1 -0 metaprl-branches/lm_libmojave/theories/experimental/compile/Makefile
+21 -0 metaprl-branches/lm_libmojave/theories/experimental/compile/m_standardize.ml
+1 -0 metaprl-branches/lm_libmojave/theories/experimental/compile/m_standardize.mli
Added metaprl-branches/lm_libmojave/theories/experimental/compile/m_x86_coalesce.ml
Properties metaprl-branches/lm_libmojave/theories/experimental/compile/m_x86_coalesce.ml
Added metaprl-branches/lm_libmojave/theories/experimental/compile/m_x86_coalesce.mli
Properties metaprl-branches/lm_libmojave/theories/experimental/compile/m_x86_coalesce.mli
+14 -8 metaprl-branches/lm_libmojave/theories/experimental/compile/m_x86_regalloc.ml
+1 -0 metaprl-branches/lm_libmojave/theories/experimental/compile/m_x86_regalloc.mli